1. Field of the Invention
The present invention relates to microcomputers such as those generally used, in particular, for the control of the operation of internal combustion engines or of antilock braking systems of motor vehicles.
It relates, more particularly, to the time management modules associated with the aforementioned microcontrollers.
The majority of the microcontrollers used in the motor vehicle industry require a time management module.
In certain applications, such as the control of the operation of the engine and the control of the antilock braking system of a vehicle, the time management module constitutes the core of the system.
The conventional advanced microcontrollers permit this type of function, but in return for an extensive involvement of the processor which is associated with them.
This is reflected in a lack of precision of the time management and in a prohibitive level of occupancy of the processor.
The functions performed by the high speed control and acquisition module comprise the acquisition function and the control function.
The acquisition function consists in measuring with precision the instant at which a change of condition takes place on an external input E.
The existing conventional solutions utilize:
a time base generally consisting of a sixteen-bit counter which is self-incremented at all resolutions; PA1 a storage zone consisting of one or of a plurality of independent registers, the number of bits of which is equal to that of the time base; PA1 a detection logic permitting the detection of a change of condition; PA1 an interrupt generation logic. PA1 a storage by means of 16-bit dedicated registers of the blocking type; PA1 a storage by means of registers organized in FIFO (first in, first out), the storage taking place in a predefined order. PA1 E1.fwdarw.CAPTURE 1 (16 bits) PA1 E2.fwdarw.CAPTURE 2 (16 bits) PA1 a time base consisting of a 16-bit counter which is self-incremented at all resolutions; PA1 a storage zone consisting of independent registers, in which zone an associated central processing unit programs the instant at which the action must take place; PA1 a 16-bit comparison logic permitting the detection of a coincidence between the value of the time base and the instant of the action; PA1 a very elementary action logic permitting the modification of the condition of the output S to which the entire control function is referred. PA1 a) 1 time counter PA1 b) 1 companion register COMP1 fixing the cycle ratio PA1 c) 1 comparison register COMP2 fixing the frequency while resetting to zero the time counter. PA1 the said switched register zone comprises a memory plane, an interface for connection with the processor, an interface for connection with the memory control logic, a decoder of addresses of the processor, a decoder of addresses of the memory control logic, and a unit for allocation of processor time intervals. PA1 The interface for connection with the processor of the switched register zone comprises a multiplexer and a demultiplexer which are connected to the switched register plane and controlled by address signals present on an address bus and transmitted to the said multiplexer and demultiplexer by a first blocking register, the multiplexer being connected to a data bus by a second blocking register and the demultiplexer being connected to the data bus by a blocking register, the said first blocking register being also connected to the decoder of addresses of the processor. PA1 The interface for connection with the memory control logic comprises a blocking register connected to a bus for connection with the memory plane, the output of the said blocking register forming the data output of the interface, a three-state interface circuit receiving the DATA IN input data, a three-state interface circuit which receives the DATA IN input data, the interface circuits being controlled by the signals CPUACK, Q13, W2 and being connected to the bus for connection with the memory plane. PA1 The unit for allocation of processor time intervals comprises a first flip-flop, the input of which receives the signal for validation of access, two MEMCNT access cycles, a set of gates for the formulation of an action signal CK from the read/write and selection signals CPU R/W and SELECT, a second flip-flop which receives the same signal CK which is connected to the output of the first flip-flop, the said second flip-flop delivering the signal of validation CPUACK of access to the central processing unit. PA1 The action unit comprises a device for the interpretation of the commands to set up virtual counters EXCHG, a device for the interpretation of the normal commands, a device for synchronization of the actions and a device for establishing the interlaced mode of scanning of the control zone. PA1 The input unit comprises a device for the detection of a change of condition on one of its inputs, for the generation of capture request signals to the address generator unit, signals which permit having simultaneously captures in buffer zone and in dedicated register and a device for the generation of event signals EVENT, INCOFF to the time base, EVENT designating that an event is in progress and INCOFF permitting the assurance, to within one resolution, of the synchronization of the external events. PA1 The serial interface unit comprises a reception device ensuring the functions of storage on reception, of storage during the synchronization phase, of time management and of word synchronization, and a transmission device ensuring functions of storage on reception, of time management and of word synchronization, and in that the unit participates as a peripheral unit, the time-management function of which is ensured by the time base unit. PA1 The interrupt unit satisfies the requests of the control function, of the acquisition function and of the serial interface function, and comprises means for ensuring the relative priorities of the said functions, means for validating interrupt and control requests, the priorities of which are reallocatable in a dynamic manner, means for ensuring the acquisition interrupt functions, means for ensuring the serial interface interrupts, and means for determining the priorities of the capture interrupts. PA1 The memory plane of the said switched register zone is a RAM memory having memory cells including MOS transistors having a number of columns at least equal to the number of bits defining the format of a control command and with time division, by utilization of the dead times of the switched register zone, the said memory plane being accessible to a source 1 consisting of the processor and to a source 2 consisting of a control logic (LCM) of the said memory. PA1 In the switched register zone there is defined a structure of virtual counters, either time or event, which can be declared in a command, these being incremented directly in switched register zone, and being readable and modifiable by the processor in this zone. PA1 The address generator intended to deliver to the switched register zone the necessary addresses in the course of an access of the memory control logic, comprises means for the generation of addresses with a view to acceding to the write zone of the said switched register zone, means for the generation of addresses with a view to acceding to the read or control zone of the said switched register zone, these accesses permitting acceding to the commands in the control zone and to instructions, and means ensuring a memory selection of the type P among N, as well as means for the generation of selective write signals in the said switched register zone. PA1 The sequencer intended to manage the interlinkings and the conflicts between the accesses emanating from the central processing unit, from the control zone or from the acquisition zone to the switched register zone comprises programmable means for division by n, means for the generation of signals STARTSCAN, FRBIT0, FRBIT1, for synchronization of scanning, means for the generation of condition signals CAPACK+COUNT UPDATE, CPUACK, CONTROL ACK, CAPACK, CAPCYC, ACK-1, means for the generation of validation signals CONTROL STROBE, RESOL, and means for the generation of sequence management signals STEP 1, CLEAR EXCHG, VIRTUAL UPDATE, the assembly making the reference time unit programmable and ensuring the optimal utilization of the available time.
The acquisition operation consists in capturing the value of the time base in the storage zone at the moment of the change of condition on the input E.
The detection logic is of the programmable type and permits the detection of a change of condition from 0 to 1 or from 1 to 0 and the generation of an activation signal.
In the time base, the usual sixteen-bit counter is incremented by an internal or external clock.
In the accumulation mode, it is likewise possible that the counter ensures the counting of an internal clock validated by an external signal.
The modification of the value of the counter is ensured by a set to zero by a software command or by a set to zero by a change of condition on an input.
There are two types of storage:
These two types of storage are mutually exclusive.
The generation of interrupts is ensured to the microprocessor in the course of the detection of a change of condition.
The disadvantages of the known devices ensuring the acquisition function are the following.
The detection logic does not permit, without a new programming of the process, the activation of the capture function both on a rising front and on a descending front of the input signal E.
It does not permit information of the EVENT type to be given to the processor.
In fact, within the context of cyclic information items and after synchronization by the processor, no information is available to indicate, without intervention of the processor, what is the event in progress.
Accordingly, the concept of event is only localized in the conventional approach.
As regards the time base, to avoid an excessively large number of logic gates, the length of the available information item (16 bits) is too limited.
This limitation requires on the part of the processor a demanding management of the counter overflows.
On the other hand, there is no direct possibility of synchronization of the time counter onto the event counter; this leads to the necessity to undertake shift corrections.
If consideration is given, for example, to a cyclic information item on six events, and if the overflow of the time counter is designated ovf, the result is the following scheme. ##STR1##
While the desired case would be: ##STR2##
The storage zone is constructed of non-general-purpose registers, and it is consequently very costly, on account of its large size.
Outside the computation zone, numerous instructions concerning the displacement of data are therefore necessary in order to process the information items acquired.
Thus, the efficiency of the software is reduced.
The quantity of information items is reduced solely to the value of the counter.
The format of the data is fixed: generally 16 bits or 16 bits+source in the case of a FIFO.
The buffer and the dedicated storage zones are not available simultaneously.
With a dedicated storage zone, an event on an input E1 involves the updating of a storage zone CAPTURE 1 allocated to the input E1.
Likewise, an event on an input E2 involves the updating of a storage zone CAPTURE 2 allocated to the input E2.
With a capture buffer, an event on an input Ei involves the storage of the value of the time base in the buffer, while the source which has given rise to the capture is indicated in an auxiliary field.
The corresponding pointer is then incremented for the next capture. ##STR3##
The solution of the buffer permits a rapid acquisition which is not limited by the processing speed of the processor.
The dedicated solution permits a direct access to the information item sought and thus the optimization of the access.
However, in order to ensure a maximum-efficiency, it would be essential to have these two solutions available simultaneously.
In the opposite case, in order to avoid any loss of information items, it is necessary to process the slow events at the same rate as the rapid events.
The control function consists in generating a set of outputs with time delays, in which each change of condition may be programmed to within one resolution.
A device for carrying out this control function comprises:
In the conventional systems, the control function is in all cases very simple.
It consists in a change of condition of an output with or without setting to zero of the time base. The most widespread type of output consists of PWM signals formed of width-modulated pulses, which are signals having programmable frequency and cycle ratios.
Such an output requires:
It will be noted that, for two PWM signals of differing frequencies, it is not possible to use the same counter as time base.
Consequently, in order to permit the wide implementation of this type of signals, it is necessary to be able to have available a large number of counters for the control functions.
The major disadvantage of all the conventional solutions resides in the fact that any multiplication by N of the number of control functions involves a multiplication by N of the associated circuits.
The elementary action logic does not permit sophisticated commands.
It is programmable, but only in non-general-purpose registers.
It is, by construction, associated in a unique and definitive manner with an output.
The time base comprises a single counter or a limited number of counters.
The counters are real, and therefore very costly in silicon.
They are accessible at dedicated addresses, outside the computation zone, and consequently the processing of their content cannot be optimized.
There is no interaction between the references of the control time base and the events of the acquisition part.
This prohibits the event/time comparisons, the interpolations between events and the direct measurements of speed.
The storage zone is associated, by construction, in a unique and definitive manner with an output.
It is constructed of non-general-purpose registers and it is therefore very costly, by reason of its large size.
Outside the computation zone, numerous instructions concerning the displacement of data are therefore necessary.
The quantity of information is reduced solely to the value of the counter.
The comparison logic permits only 16-bit time comparisons and it is, in particular, incapable of detecting conditional instants (event/time).
The object of the invention is to remedy the aforementioned disadvantages of the known devices by creating a time management device integrated with a microcontroller which carries out the said time management by virtue of a set of programmable acquisition, control and correlation functions, articulated about a flexible and inexpensive memory organization.